1. Field of the Invention
This invention relates to the gathering of resistance and capacitance data from integrated circuit designs from multiple foundries as input to computer aided design tools, which can provide circuit analyses. These analyses include coupling noise, electromagnetic interference generation, power dissipation, and resistive voltage drop. More particularly, this invention relates to the automatic generation of resistive/capacitive technology data files, which are converted to formats usable by computer aided design analysis programs from a generic technology file.
2. Description of Related Art
Today, integrated circuit designers must use design automation tools for analysis of semiconductor circuits. The various analyses 170 include noise coupling analysis, resistive voltage drop calculation, determining electromagnetic interference effects, circuit delay calculation, and power dissipation analysis. These analysis tools come from different design automation tool providers. As shown in FIG. 1, a typical circuit designer may deal with multiple foundries 100, 110, 120 to fabricate their designs. Each foundry 100, 110, 120 provides the process parameters that determine the resistivity and dielectric contants of the materials employed in fabricating an integrated circuit in the semiconductor process. The foundries may differ in their minimum possible line widths or in the type of dielectric material used to make capacitors for example. In addition, the circuit designer utilizes computer aided design analysis applications or tools 130, 140, 150, 160 from different vendors. It is the designer""s responsibility to supply the required input information, such as resistivity, dielectric, and other physical properties) from the semiconductor foundries to the computer aided analysis tools. The results from the analysis tools are only accurate and useful if the required material properties are accurate and correct. Typically, the circuit designer has to manually prepare technology data files which gather information such as the resistivity, dielectric constants, wiring lengths and widths, oxide thickness from the foundries 100, 110, 120 and provide this information in the varied formats required by the different computer aided analysis tools providers. As shown in FIG. 1, four different Technology Data Files (TDF) 125, 135, 145, 155 may be required per chip coming from a single foundry. If the chip is fabricated at two foundries, the number of TDF files the circuit designer must generate would be eight. If the chip is fabricated at three foundries, the number of TDF files the designer must generate would be twelve, as shown.
Referring now to FIGS. 2a, 2b, and 2c for a discussion of the information contained within a technology description file (TDF) 400 necessary for calculation of capacitance and resistance of semiconductor structures that form integrated circuits. FIG. 2a illustrates a header structure for a TDF 400. The header structure provides a technology name describing the process to be used within the foundry 100, 110, 120 described by the technology data file 400. The header has a label for the tolerance level or CASE of the detail dimensions of the technology described. The tolerance level or CASE will either be xe2x80x9cnormal,xe2x80x9d xe2x80x9cbestxe2x80x9d, or xe2x80x9cWorstxe2x80x9d case. The header further contains a title detailing more information about the process of the foundry 100, 110, 120. The header also contains a revision code and data to chronicle changes in the TDF 400. The intended modeling tool is described. In this example SPICE, a circuit level simulation program well known in the art, is named as the target modeling tool. The SPICE circuit model description file is the source of the TDF. The name of the author(s) of the TDF 400 identifies the person responsible for creating and revising the TDF 400.
FIG. 2b describes the contents of the TDF 400 for the dielectric insulation layers used to isolate conductive layers used in forming and interconnecting the electronic components of the integrated circuit. The statement demarcated by the double backward slash marks (//) indicate comments describing the fields of the TDF 400. The text //type describes the type of material specified. The dielectric material is denoted with a D, a conductor is denoted with a C, the diffusion layers are noted with an F, and a passivation layer is denoted with a P.
The dielectric constant (die-c) is itemized for each type of insulating material by layer that is used. The thickness is described, as is the variation in the thickness as a percentage of the thickness.
The diffusion layers are described giving the depth within the semiconductor substrate for the diffusion, the minimum thickness of the diffusion, the minimum dimensions (MinW) of the diffusion, the minimum spacing (MinS) between diffusions, the resistivity of the diffusion material, and a bias or difference between the designed or drawn dimensions and the actual fabricated dimensions.
FIG. 2c illustrates the TDF 400 entries for conductors placed on a semiconductor substrate to interconnect the electronic devices of the integrated circuit and to form the gate structures of field effect transistors (FET""s) of the integrated circuit. The specification of the TDF 400 for conductors include the height above the substrate for each conductor, the thickness of the conductors, the minimum dimensions (MinW) of the conductor, the minimum spacing between conductors (MinS), the resistivity of the conductors, a bias factor for the difference between the designed or drawn dimensions and the actual dimensions, the overlaying dielectric layer (ABOVE), and the variations as a percentage of the thickness and width of the conductor (3d1, 3d2).
The description of the via contacts or interlayer connection for conductors includes the resistance (ohm/ct) for each via contact, the width and length of the via contact, the name of the lower conductor (low-m), and the name of the upper conductor (upper-m).
As is understood by a person skilled in the art, the TDF 400 as shown provide sufficient information for calculating the resistance of the conductive layers and the diffusions, and the capacitance formed between any of the conductive layers. Further, the TDF 400, as shown, is used as a source document and is translated to the format acceptable as technology files for commercially available computer aided design programs
xe2x80x9cVerification of Circuits Described in VHDL Through Extraction of Design Intent,xe2x80x9d Hoskote et al, Proceedings of the Seventh International Conference on VLSI Design, IEEE, January, 1994, pp. 417-420, describes a verification framework to verify VHDL designs from the scheduled behavioral level down to the gate level by capturing the design intent, on the basis of a formal semantics, in a form appropriate for input to the verifier.
xe2x80x9cEfficient Net Extraction for Restricted Orientation Designs [VLSI Layout],xe2x80x9d Lopez et al., IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Sept. 1996 Vol. 15 Issue: 9 ISSN: 0278-0070, pp. 1151-1159 describes an algorithm to extract a physical net description based on the intersections of connections within a net.
U.S. Pat. No. 6,009,252 (Lipton) teaches a layout versus schematic(LVS) comparison tool determines one-to-one equivalency between an integrated circuit schematic and an integrated circuit layout by performing operations to generate color symmetric matrices corresponding to respective child cells in the integrated circuit schematic.
U.S. Pat. No. 5,452,224 (Smith, Jr. et al.) describes a method for computing parasitic capacitances between multiple electrical conductors within an electric circuit. The parasitic capacitances associated with the conductors of each window are computed, and the results for the various windows combined into a matrix of parasitic capacitances for the overall circuit.
U.S. Pat. No. 5,706,206 (Hammer, et al.) describes a method for extracting parasitic capacitance values from the physical design of an integrated circuit. More particularly, lateral coupling and fringing capacitance values are extracted from the physical design of an integrated circuit.
U.S. Pat. No. 5,999,010 (Arora, et al.) describes a method for measuring the coupling capacitance between two interconnects lines of an integrated circuit structure having a ground plane.
It is an object of this invention to provide a method for providing a description of process dependent circuit parameters of integrated circuit technology that is acceptable to computer aided design tools from different design automation tool providers for automatically modeling and verifying integrated circuit designs.
To accomplish this and other objects, a method for generating technology data files for use by at least one chip and circuit analysis tools begins by accepting at least one user analysis request for a specific chip and circuit analyses. The specific chip and circuit analyses to be performed are power dissipation calculation, electromagnetic noise coupling determination, resistive voltage drop calculation, and circuit delay analyses. The design automation tool required for the requested analysis is then selected. A standard, generic technology data file(TDF) is converted to a custom TDF specified for a given design analysis tool from a set of TDF formatting rules for the given design analysis tool. The chip coordinate references, process parameters and line segment layout data to be tested are extracted from a physical design data layout file. The line segment layout data of a standard wafer test site for the foundry/process selected is extracted from a circuit simulation model of the desired foundry/process. The design automation tool is executed using the foundry process and layout data as requested in the user analysis request. An analysis specified by the user analysis request is executed with the selected design automation tool using the foundry process and layout data of the standard wafer test site. The results of the analysis using the foundry process and layout data of the standard wafer test site are compared with the actual data describing the test site function. An error report is issued to the circuit designer if the verification of the analysis of the standard test site fails to match the known test site result. However, a positive report is issued to the circuit designer if the verification the analysis of the standard test site does match the known test site result, The requested analysis results report is released for further use if the verification analysis of the standard test site does match the known test site result.
The method further provides a user interface to request the analysis type of specific circuit or set of interconnected circuits on a specific integrated circuit chip to be fabricated at a specific foundry, the integrated circuit chip coordinate reference and the line segment layout data, and the foundry process parameters and circuit coordinates on the chip. The requested analysis type, integrated circuit chip circuit coordinate reference and the line segment layout data, and the foundry process parameters and circuit coordinates on the chip is separated. and the analysis tool required to deliver the user analysis request is selected. The physical dimensions are prepared. The physical dimensions are the line lengths and line widths, line thickness, and oxide thickness from the line segment layout data of the circuit or circuits to be analyzed. The foundry chip circuit simulation model is extracted from the integrated circuit design database and a generic technology data file (TDF) is created from the circuit simulation model. A set of predetermined analysis results of a standard test site are extracted for verifying the results of the selected analysis.